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W99685BS Data Sheet SYSTEM CAMERA DEVICE
Table of Contents1. 2. 3. GENERAL DESCRIPTION ......................................................................................................... 2 FEATURES ................................................................................................................................. 2 APPLICATION ............................................................................................................................ 6 3.1 3.2 3.3 4. 4.1 4.2 5. 5.1 5.2 5.3 System Overview ............................................................................................................ 6 Host Interface ................................................................................................................. 6 Camera Implementation ................................................................................................. 8 W99685BS Pin Definition (81 Balls, LFBGA Package) .................................................. 9 W99685BS-81b Pin Assignment - Top View ............................................................... 12 Absolute Maximum Ratings .......................................................................................... 14 D.C. Characteristics...................................................................................................... 15 A.C. Characteristics ...................................................................................................... 15
5.3.1 5.3.2 5.3.3 5.3.4 RESET A.C. Characteristics...........................................................................................15 Video Input A.C. Characteristics.....................................................................................16 Host Interface: CF-IDE Slave (Memory Bus) A.C. Characteristics .................................17 LCD Interface A.C. Characteristics.................................................................................18
PIN DESCRIPTION..................................................................................................................... 9
ELECTRICAL CHARACTERISTICS......................................................................................... 14
6. 7.
PACKAGE DIMENSION ........................................................................................................... 19 6.1 81L LFBGA (8 x 8 mm, Ball pitch: 0.8 mm, O = 0.4 mm) ............................................. 19 REVISION HISTORY ................................................................................................................ 20
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Publication Release Date: April 12, 2005 Revision A4
W99685BS
1. GENERAL DESCRIPTION
W99685BS is a high performance and highly-integrated system camera device that it can preview, capture, compress, store, and display the digital still images or playback a short period of live video. This chip provide 8 or 16 Bits Host interface and easy for base band platform( Host ) to develop Camera function through Winbond CF Command set protocol that allow the development of products without knowing any W99685BS chip programming. W99685BS Built-in 8-bit 8032 compatible uC with internal 16KB program RAM and 4K data RAM. Program can be down load from memory bus interface. This chip also Built-in 2M byte frame buffer for real-time video clip (MJPG) and burst snapshot. Support CCIR-656 8-bit YUV CMOS or CCD capture sensor interface. W99685BS Support up to dual LCD Panels interface with MCU type interface. Support TFT-LCD, CSTN-LCD, STN-LCD Panel Types , If camera function is active, the host CPU can use W99685BS as the bridge (display controller) to LCM. And it can provide multiple display buffers. If camera function is disabled, the host CPU can use bypass mode to control the LCM directly for maximum power saving. W99685BS Support dual video pipes and double buffering for real-time motion JPEG, Support smooth scaling-down of video pipes, different kinds of raw data formats for display, some popular image color effects ( Black & White,Sepia,Negative,Solarize or Oil Painting ), video rotation/mirror/flip for capture and playback,sticker maker, Comic Photo maker and smart frame rate control.
2. FEATURES
General * * * * 0.18um logic process Core 1.8V I/O 2.6V - 3.6V Power consumption - - * * * * * * * * < 23mA for 160x120 @ 15 fps, 2.8V preview mode < 35mA for 160x120 @ 30fps, 2.8V preview mode
Support power-down mode Support LCD bypass mode Support GPIO pins for flash light control or else Built-in smart processor to allow the development of products without knowing any W99685 chip programming. Minimum product design cycle time for fast time-to-market Built-in 8-bit 8032 compatible uC with internal 16KB program RAM and 4K data RAM Program can be down load from host interface. Built-in 2M bytes frame buffer for real-time video clip (M-JPEG) and burst snapshot. Support VGA/ Mega image resolution
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W99685BS
Sensor Interface * Support CCIR-656 8-bit YUV interface * Supports fast serial interface to program image sensor. Host Interface * 8/16 bits parallel Bus (Indirect access) Easy for base band chip( Host ) to develop Camera function through Command set protocol. LCD Display Interface * Support up to dual LCD Panels interface * Supports MCU type interface LCD module * Supports 8/16/18-bit display data output to LCD Penal * Support 4 kinds of display data format out to LCD Penal - - - - 256 colors (RGB-332) 4096 colors (RGB-444) 64k colors (RGB-565) 256k colors (RGB-666)
* Support LCD interface bypass mode * Support TFT-LCD, CSTN-LCD, STN-LCD Panel Types * * If camera function is active, the host CPU can use W99685BS as the bridge (display controller) to LCM. And it can provide multiple display buffers. If camera function is disabled, the host CPU can use bypass mode to control the LCM directly for maximum power saving.
JPEG CODEC for Image Compression and Decompression * Fully compliant with ISO/IEC 10918-1 international JPEG standard * JPEG compression and decompression for still images * Real-time motion JPEG (M-JPEG) compression with advanced bit rate control for live video * JPEG baseline sequential mode in interleaved scan YcbCr(4:2:2) or YcbCr(4:2:0) format * Support adjustable quantization table for different compression ratio * Support smooth digital zoom * Support JPEG re-sizing and re-encoding
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Publication Release Date:April 13, 2005 Revision A4
W99685BS
Operation Modes * * * * * * * * Preview ModeFrame rate up to 30 fps Single Snapshot Mode Burst Snapshot Mode - - Support up to 10 frames burst snapshot at 1/30 sec interval About 15 seconds recording time with 800K bytes vedio buffer at 160x120 size @ 15 fps Movie Mode (Motion JPEG) Playback Mode Comic Photo Mode Transfer Mode Still Image Size - - - - - * - 1280 x 960 640 x 480 (VGA) 320 x 240 (QVGA) 160 x 120 (QQVGA) Subject to change by request 160x120 (QQVGA)
Video Clip Size
Video Display Function * * * * * * * Support high-color / OSD Video overlay function Support graphics/video blending Support image Rotation / Flip / Mirror Left 90 degree rotation Right 90 degree rotation 180 degree rotation Horizontal mirror
* Vertical flip * Support image color effects * Normal * Black & white * Sepia * Negative * Solarize / oil painting * Support image sticker maker * Support imprint of message photo -4-
W99685BS
* Support comic photo maker * Support OSD Video overlay function * * * * * Support dual video pipes and double buffering for real-time Motion JPEG Support arbitrary N/M (=[0..255]) scaling-down of video pipes Support different kinds of raw data formats for display Support some popular image color effects Support smart frame rate control
Power Management * Advanced power management including: - Power-down mode - Stand-by mode - Operating mode
Package: * W99685BS/ BGA 81-Balls package (8mm x 8mm)
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Publication Release Date:April 13, 2005 Revision A4
W99685BS
3. APPLICATION
3.1 System Overview
Sensor
W99685BS
(single chip DSC controller)
LCM (MAIN)
LCM (SUB)
IDE/Memory Bus
Mobile Phone or PDA Host
3.2 Host Interface
Host Interface IDE * High speed parallel bus (8-bit or 16-bit) * Ideal attachable CF camera solution especially for PDA with CF slot * Ideal built-in camera solution Host Interface IDE-1 [A3..A1] [D7..D0]
Host CPU
W99685BS
RD# WR#
CS#
LCM1
LCM2
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W99685BS
Host Interface IDE-2
[A4..A1] [D15..D0] [D15..D0] RD#
Host CPU
RD# WR# CS#
WR#
LCM1
W99685BS
R/S# LCS1#
LCM2
R/S# LCS2#
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Publication Release Date:April 13, 2005 Revision A4
W99685BS
3.3 Camera Implementation
Preview Mode Features * * * * * * Support raw data preview or JPEG preview Support video preview directly to LCM Support video rotation/flip/mirror Support live color effect and sticker display Support up to 30 fps preview depending on the sensor frame rate Support digital zoom
Snapshot Mode Features * * * * * * Support encoding of different size of images Support image rotation/flip/mirror Support color effect and sticker functions
Burst Snapshot Mode Features Extension to snapshot (single capture) mode Support up to 10 frames burst snapshot at 1/30 sec interval The encoded pictures are stored in W99685 frame buffer, the host can select the favorite ones for storage.
Movie Mode Features * * * * Support real-time video clip encoding The video clip (dumb video) is stored in W99685 frame buffer, the duration depends on the frame rate and resolution Dumb Video Implementation Motion JPEG Movie Implementation
Playback Mode Features * * * * * * * Support still JPEG playback directly to LCD or raw data Support motion JPEG video playback direct to LCD or raw data Support image rotation/flip/mirror Support playback mode digital zoom in for 1.0x~2.0x to raw data or 1.0x~7.999x to LCD at small steps Support playback mode digital zoom out to LCD or raw data at N/M (=[0..255]) Support pan/tilt control for LCD output at zoom in Support JPEG re-sizing and re-encoding
Comic Photo Mode Features * * Support MxN grids of comic photo Each grid of comic photo can come either from a stored JPEG file or a captured video frame.
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W99685BS
4. PIN DESCRIPTION
4.1 W99685BS Pin Definition (81 Balls, LFBGA Package)
The following signal types are used in these descriptions. I IS B BR BU O A P G # Input pin Input pin with Schmitt trigger Bi-directional input/output pin Bi-directional input/output pin with repeater Bi-directional input/output pin with internal pull-up Output pin Analog input/output pin Power supply pin Ground pin Active low
UART Interface (2 pins)
PIN NAME PIN NUMBER TYPE DESCRIPTION
TXD / P3[1] RXD / P3[0]
J5 H5
B B
Serial Transmit Data Port-3 Bit-1 Serial Receive Data Port-3 Bit-0
Sensor or Video Input Interface (14 pins)
PIN NAME PIN NUMBER TYPE DESCRIPTION
SVID[9:0] SPCLK SVS SHS SCLK
G7, A5, B5, C5, J8, H8, A6, B6, C6, H9 B4 H7 J7 A4
I I B B O
Sensor or Video Data Input SVID[9:0]. Clock for Sensor or Video Data Input Vertical Sync Input. Programmable polarity. Horizontal Sync Input. Programmable polarity. Clock Output to Sensor
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Publication Release Date:April 13, 2005 Revision A4
W99685BS
LCD Digital Display Interface (19 pins) & Power on Setting (8 pins)
PIN NAME PIN NUMBER TYPE DESCRIPTION
LA0(R/S) LCD_CS0# LCD_WR# LDATA [7:0]/ Setting [7:0] LDATA [15:8]
D8 B7 A7 E7, D9, F7, C9, G8, F9, D7, E9 B8, A8, A9, C8, E8, B9, G9, F8
O O O BU BU
M-LCD: Address-0, for LCD Controller RS signal (CMD/DAT#) M-LCD: LCD Chip Select M-LCD: Write Enable Digital Display Output Data 8 bits Power On Setting [7:0] Digital Display Output Data [15:8 ]bits 0 enable
Host Interface (23 pins)
PIN NAME PIN NUMBER TYPE DESCRIPTION
FA0 FA1 FA2 FIORD# FIOWR# FCE2# / LCD_CS# FCE1# FD [15:0]
B1 J6 C1 D2 E3 E2 D1 A2, A1, C2, J4, B2, C3, B3, A3, H3, H4, F2, E1, G3, G4, G5, F3
BR BR BR BU BU BR BR BR
Address-0 Address-1 Address-2 I/O Read Strobe I/O Write Strobe Chip Select Signal - 2 LCD Function Selected Chip Select Signal - 1 Data Bus FD[15:0]
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W99685BS
GPIO (6 pins)
PIN NAME PIN NUMBER TYPE DESCRIPTION
GPIO0 GPIO1/ LCD_CS1# GPIO2/ GPIO3/ SCK GPIO4/ SDI/SDA GPIO5/ SDO/SDE
J3 G1 D3 C4 G6 H6
BU BU BU BU BU BU
General Purpose I/O [0] General Purpose I/O [1] M-LCD: LCD Chip Select General Purpose I/O [2] General Purpose I/O [3] Serial Interface Clock General Purpose I/O [4] Serial Interface Data Input/ Serial Data Acknowledge General Purpose I/O [5] Serial Interface Data Output / Serial Data Enable 1 enable
Miscellaneous (4 pins)
PIN NAME PIN NUMBER TYPE DESCRIPTION
XIN XOUT RESET TME
G2 F1 H1 J1
I O IS I
Reference frequency input from ext. crystal or a clock source. Oscillator output to a crystal. This pin is left unconnected if an external clock source is employed. Reset In. This pin is active high to reset W99685 chip. Test Mode Enable. Only for test, this pin must be connected to GND for normal operation.
Power and Ground (13 pins)
PIN NAME PIN NUMBER TYPE DESCRIPTION
VDDB GND VDDI AVDDP AVSSP VDDFB
C7, E6, J9 D4, D6, E5, F4, F6 D5, F5 J2 H2 E4
P G P P G P
I/O Pad Buffer Power Supply. Provide isolated power to the I/O buffers for improved noise immunity. 2.6V~3.6 V. I/O Pad Buffer Ground. Internal Core Logic Power Supply. 1.8 V . PLL Power Supply. 1.8 V . PLL Ground. Embedded Frame Buffer Power Supply. 2.6V~3.6 V.
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Publication Release Date:April 13, 2005 Revision A4
W99685BS
4.2 W99685BS-81b Pin Assignment - Top View
A1 CORNER 1 2 3 4 5 6 7 8 9
A
FD14
FD15
FD8
SCLK
SVID8
SVID3
LCD_WR #
LDAT14
LDAT13
B
FA0
FD11
FD9
SPCLK
SVID7
SVID2
LCD_CS0 #
LDAT15
LDAT10
C
FA2
FD13
FD10
GPIO3 / SCK
SVID6
SVID1
VDDB
LDAT12
LDAT4
D
FCE1#
FIORD#
GPIO2
GND
VDDI (1.8V)
GND
LDAT1
LA0(R/S)
LDAT6
E
FD4
FCE2#/ LCD_CS #
FIOWR#
VDDFB
GND
VDDB
LDAT7
LDAT11
LDAT0
F
XOUT
FD5
FD0
GND
VDDI (1.8V)
GND
LDAT5
LDAT8
LDAT2
GPIO1/ G LCD_CS1 # XIN FD3 FD2 FD1
GPIO4 / SDA
SVID9
LDAT3
LDAT9
H
RESET
AVSSP (GND)
FD7
FD6
RXD / P_30
GPIO5 / SDO
SVS
SVID4
SVID0
J
TME
AVDDP (1.8V)
GPIO0
FD12
TXD /P_31
FA1
SHS
SVID5
VDDB
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W99685BS
W99685BS 81 Ball Location List
LOCATION/ NUMBER PIN NAME LOCATION/ NUMBER PIN NAME
C7 / (1) D3 / (2) D2 / (3) E3 / (4) E2 / (5) D1 / (6) D4 / (7) F3 / (8) G5 / (9) G4 / (10) G3 / (11) E1 / (12) F2 / (13) H4 / (14) H3 / (15) J3 / (16) G2 / (17) F1 / (18) G1 / (19) H2 / (20) J2 / (21) J1 / (22) H1 / (23) H5 / (24) J5 / (25) E6 / (26) D6 / (27) D5 / (28) E5 / (29) E9 / (30)
VDDB(2.6V~3.6V) GPIO2 FIORD# FIOWR# FCE2# / LCD_CS# FCE1# GND FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 GPIO0 XIN XOUT GPIO1 / LCD_CS1# AVSSP(GND) AVDDP(1.8V) TME RESET RXD / P3_0 TXD / P3_1 VDDB(2.6V~3.6V) GND VDDI(1.8V) GND LDAT0 / SET0
E8 / (42) C8 / (43) A9 / (44) A8 / (45) B8 / (46) J9 / (47) D8 / (48) B7 / (49) A7 / (50) F4 / (51) H9 / (52) C6 / (53) B6 / (54) A6 / (55) F6 / (56) H8 / (57) J8 / (58) C5 / (59) B5 / (60) A5 / (61) G7 / (62) B4 / (63) H7 / (64) J7 / (65) A4 / (66) C4 / (67) G6 / (68) H6 / (69) A3 / (70) B3 / (71)
LDAT11 LDAT12 LDAT13 LDAT14 LDAT15 VDDB(2.6V~3.6V) LA0(R/S) LCD_CS0# LCD_WR# GND SVID0 SVID1 SVID2 SVID3 GND SVID4 SVID5 SVID6 SVID7 SVID8 SVID9 SPCLK SVS SHS SCLK SCK / GPIO3 SDA / GPIO4 SDO / GPIO5 FD8 FD9
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Publication Release Date:April 13, 2005 Revision A4
W99685BS
W99685BS 81 Ball Location List, continued
LOCATION/ NUMBER
PIN NAME
LOCATION/ NUMBER
PIN NAME
F5 / (31) D7 / (32) F9 / (33) G8 / (34) C9 / (35) F7 / (36) D9 / (37) E7 / (38) F8 / (39) G9 / (40) B9 / (41)
VDDI(1.8V) LDAT1 / SET1 LDAT2 / SET2 LDAT3 / SET3 LDAT4 / SET4 LDAT5 / SET5 LDAT6 / SET6 LDAT7 / SET7 LDAT8 LDAT9 LDAT10
C3 / (72) B2 / (73) J4 / (74) C2 / (75) A1 / (76) A2 / (77) B1 / (78) J6 / (79) C1 / (80) E4 / (81)
FD10 FD11 FD12 FD13 FD14 FD15 FA0 FA1 FA2 VDDFB(2.6V~3.6V)
5. ELECTRICAL CHARACTERISTICS
5.1 Absolute Maximum Ratings
PARAMETER MIN. MAX. UNIT
Ambient temperature Storage temperature DC supply voltage for core (1.8V) VDDI DC supply voltage for I/O (2.8V) VDDB I/O pin voltage with respect to VSS
Table 5-1
-20 -40 0 0 - 0.3
70 125 2.0 3.6 VDDB + 0.4
C C V V V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
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W99685BS
5.2 D.C. Characteristics
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VDDB AVDDP VDDI VIL VIH VOL VOH VOH (P30/P31) IIL IIH IUP IPD
Power Supply for I/O Pads Power Supply for PLL Analog Power Supply for Core Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage (Open Drain with Internal Pull- IOUT = -2 mA Up) Input Low Leakage Current Input High Leakage Current Pull-up Current Power Down Current (XIN=0, No Load) VIN = 0.4V VIN = 2.4V VIN = 0V Core VDDI= 1.8V I/O VDDB= 2.8V 160x120 preview at 15 fps IOUT = 2mA IOUT = -2mA
2.6 1.70 1.70 0 2.0 VDDB * 0.8
2.8 1.8 1.8
3.6 1.90 1.90 0.8 VDDB VSS +0.4
V V V V V V V
2.0 10 -10 -500 20 120
V A A A A
IDD
Active Current
CPU clock at 12 MHz Engine clock at 24 MHz
Table 5-2
20
30
mA
5.3 A.C. Characteristics
5.3.1 RESET A.C. Characteristics
RSTI TRST
Figure 5.1
RESET Timing Diagram
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Publication Release Date:April 13, 2005 Revision A4
W99685BS
RESET Timing
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
TRST
Reset Pulse Width
Table 5-3
1.0
mS
5.3.2
Video Input A.C. Characteristics
TSPCLK SPCLK THIGH TLOW TSU SVID[7:0] SHS, SVS
1.5 V input valid 1.5 V
TH
1.5 V
Figure 5.2
Input Video Timing Diagram
Input Video Timing
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
FSPCLK THIGH TLOW TSU TH
SPCLK Frequency = 1 / TSPCLK SPCLK Clock High Time SPCLK Clock Low Time SVID[9:0], SHS, SVS Setup Time SVID[9:0], SHS, SVS Hold Time
Table 5-4
5 5 5 6 4
48
MHz nS nS nS nS
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W99685BS
5.3.3 Host Interface: CF-IDE Slave (Memory Bus) A.C. Characteristics
FCE1_,FCE2_ FA2:0]
TCAS TRD TCAH
FIORD#
TODD TODH Valid Data TCAS TWR TCAH
FD[15:0]
FIOWR#
TWDS TWDH
FD[15:0]
Valid Data
Figure 5.3
Host Interface: CF-IDE Slave (Memory Bus) Timing Diagram
Host Interface: CF_IDE Slave (Memory Bus) Timing
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
TCAS TCAH TODD TODH TRD TWDS TWDH TWR
Chip Select & Address Set-up Time Chip Select & Address Hold Time FIORD# Low to Data Valid Delay Read Data Output Hold Time FIORD# Pulse Width Write Data Input Setup Time Write Data Input Hold Time WR# Pulse Width
Table 5-5
65 5 --0 *165/4TMCL
K
----4TMCLK -----------
nS nS nS nS nS nS nS nS
60 2 *165/4TMCL
K
165/4TMCLK : 165ns or 4 internal engine clock cycles
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Publication Release Date:April 13, 2005 Revision A4
W99685BS
5.3.4 LCD Interface A.C. Characteristics
LCS_
TLAS TLAH
LA0
TLCSS TLWR TLCSH
80 Mode : LWR#
TLDOD TLDOH Valid Data TLE
LDATA[15:0]
68 Mode : LE
Figure 5.4
LCD Interface Timing Diagram
LCD Interface Timing
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
TLCSS TLCSH TLAS TLAH TLDOD TLDOH TLWR TLE
Chip Select Set-up Time Chip Select Hold Time Address Set-up Time Address Hold Time Write Data Active Delay Write Data Hold Time LWR# Pulse Width LE Pulse Width 80 Mode 68 Mode
Table 5-6
0.5 0.5 1 1 5 0.5 0.5 0.5
-------------
PCLK PCLK PCLK PCLK nS PCLK PCLK PCLK
Note: PCLK => Engine Clock / 32
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W99685BS
6. PACKAGE DIMENSION
6.1 81L LFBGA (8 x 8 mm, Ball pitch: 0.8 mm, O = 0.4 mm)
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Publication Release Date:April 13, 2005 Revision A4
W99685BS
7. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 A2 A3 A4
June 28, 2004 Dec. 15, 2004 Feb. 24, 2005 April 13, 2005 16 2, 4, 8 15
Initial Issue Revise Fspclk to 48 MHz Update LCD I/F, JPEG Codec Update IPD
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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